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CY7C1021V
64K x 16 Static RAM
Features
* 3.3V operation (3.0V-3.6V) * High speed -- tAA = 10/12/15 ns * CMOS for optimum speed/power * Low Active Power (L version) -- 576 mW (max.) * Low CMOS Standby Power (L version) -- 1.80 mW (max.) * Automatic power-down when deselected * Independent control of upper and lower bits * Available in 44-pin TSOP II and 400-mil SOJ * Available in a 48-Ball Mini BGA package Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8 ), is written into the location specified on the address pins (A0 through A15 ). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 9 through I/O16 ) is written into the location specified on the address pins (A0 through A15 ). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O 1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021V is available in 400-mil-wide SOJ, standard 44-pin TSOP Type II, and in 48-ball mini BGA packages.
Functional Description
The CY7C1021V is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration
SOJ / TSOP II Top View A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A7 A6 A5 A4 A3 A2 A1 A0
64K x 16 RAM Array 512 X 2048
I/O1 - I/O 8 I/O9 - I/O 16
COLUMN DECODER BHE WE CE OE BLE
1021V-1
A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
1021V-2
ROW DECODER
Selection Guide
7C1021V-10 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Commercial L Commercial L 10 210 160 5 0.500 7C1021V-12 12 200 150 5 0.500 7C1021V-15 15 190 140 5 0.500
Cypress Semiconductor Corporation
A8 A9 A10 A11 A12 A13 A14 A15
*
SENSE AMPS
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 October 18, 1999
CY7C1021V
Pin Configurations (continued)
Mini BGA (Top View)
1
BLE
2
OE
3
A0
4
A1
5
A2 CE I/O2
6
NC I/O1 I/O3
A B C D E F G H
I/O9 BHE I/O10 I/O11
A3
A5
A4
A6 A7 NC
VSS I/O12 NC VCC I/O13 NC I/O15 I/O14 A14 I/O16 NC NC A8 A12 A9
I/O4 VCC I/O5 VSS I/O7
A15 I/O6 A13 A10
WE I/O8 A11 NC
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage on VCC to Relative GND
[1]
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature[2] 0C to +70C -40C to +85C VCC 3.3V 10% 3.3V 10%
.... -0.5V to +4.6V
DC Voltage Applied to Outputs in High Z State[1] ......................................-0.5V to VCC+0.5V DC Input Voltage[1]...................................-0.5V to VCC+0.5V
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature.
2
CY7C1021V
Electrical Characteristics Over the Operating Range
7C1021V-10 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current -- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 L L Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -1 -1 Min. 2.4 0.4 VCC+ 0.3V 0.8 +1 +1 210 160 40 2.2 -0.3 -1 -1 Max. 7C1021V-12 Min. 2.4 0.4 VCC+ 0.3V 0.8 +1 +1 200 150 40 2.2 -0.3 -1 -1 Max. 7C1021V-15 Min. 2.4 0.4 VCC+ 0.3V 0.8 +1 +1 190 140 40 Max. Unit V V V V A A mA mA mA
ISB1
ISB2
5 500
5 500
5 500
mA A
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz Max. 6 8 Unit pF pF
Note: 3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.3V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 351 R 317 R 317 3.3V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 351 GND <3 ns 3.0V 90% 10% 90% 10% <3 ns ALL INPUT PULSES
(b)
1021V-3 1021V-4
167 OUTPUT Equivalent to: THEVENIN EQUIVALENT 30 pF
1.73V
3
CY7C1021V
Switching Characteristics[4] Over the Operating Range
7C1021V-10 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[5, 6] CE LOW to Low Z
[6]
7C1021V-12 Min. 12 Max.
7C1021V-15 Min. 15 Max. Unit ns 15 3 15 7 0 7 3 7 0 15 7 0 7 15 10 10 0 0 10 8 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 9 ns ns
Description
Min. 10
Max.
10 3 10 4 0 5 3 5 0 12 5 0 5 10 8 7 0 0 8 6 0 3 5 8 8 12 9 8 0 0 8 6 0 3 0 0 3 0 3
12 12 6 6 6 12 6 6
CE HIGH to High Z[5, 6] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z
[6]
WRITE CYCLE[7]
WE LOW to High Z[5, 6] Byte Enable to End of Write
6
Data Retention Characteristics Over the Operating Range (L version only)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current Com'l VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 0 tRC Conditions[10] Min. 2.0 100 Max. Unit V A
tCDR[8] tR[9]
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 30-pF load capacitance. 5. t HZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. Tested initially and after any design or process changes that may affect these parameters. 9. t r < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. 10. No input may exceed VCC + 0.5V.
4
CY7C1021V
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE
1021V-5
VDR > 2V
3.0V tR
Switching Waveforms
Read Cycle No. 1
[11, 12]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1021V-6
Read Cycle No. 2 (OE Controlled)
ADDRESS
[12, 13]
tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE V CC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB
1021V-7
tHZOE
HIGH IMPEDANCE
DATA OUT
IICC CC
Notes: 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW.
5
CY7C1021V
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)
[14, 15]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD
tHA
1021V-8
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
1021V-9
Notes: 14. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
6
CY7C1021V
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD
1021V-10
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1-I/O8 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O9-I/O 16 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power-Down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
7
CY7C1021V
Ordering Information
Speed (ns) 10 Ordering Code CY7C1021V33-10BAC CY7C1021V33-10VC CY7C1021V33L-10VC CY7C1021V33-10ZC CY7C1021V33L-10ZC 12 CY7C1021V33-12BAC CY7C1021V33-12VC CY7C1021V33L-12VC CY7C1021V33-12ZC CY7C1021V33L-12ZC CY7C1021V33-12BAI CY7C1021V33-12VI 15 CY7C1021V33-15BAC CY7C1021V33L-15BAC CY7C1021V33-15VC CY7C1021V33L-15VC CY7C1021V33-15ZC CY7C1021V33L-15VC CY7C1021V33-15BAI CY7C1021V33L-15BAI CY7C1021V33-15VI CY7C1021V33L-15ZI Document #: 38-00544-D Package Name BA48 V34 V34 Z44 Z44 BA48 V34 V34 Z44 Z44 BA48 V34 BA48 BA48 V34 V34 Z44 Z44 BA48 BA48 V34 Z44 Package Type 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) 44-Lead (400-Mil) Molded SOJ 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II Industrial Commercial Industrial Commercial Operating Range Commercial
8
CY7C1021V
Package Diagrams
48-Ball (7.00 mm x 7.00 mm) FBGA BA48
51-85096-C
9
CY7C1021V
Package Diagrams (continued)
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
44-Pin TSOP II Z44
51-85087-A
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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